IonQ runs real-time error decoding on single CPU for simulated 408 logical qubits

【Article Title】 IonQ runs real-time error decoding on single CPU for simulated 408 logical qubits 【Article Body】 AI TRANSLATION This article is an AI-generated translation of the original Japanese article. For the authoritative version, please refer to the original. Read the original Japanese article → (https://quantumindex.jp/ionq-real-time-quantum-error-decoder-single-cpu/) IonQ announced it has developed an end-to-end, real-time quantum error-correction decoder that runs on a single commercial CPU and says it successfully tested the system. Using benchmark circuits that simulated up to 408 logical qubitslogical qubitsLogical Qubit / Logical QubitA unit of information treated as a single qubit protected from errors by using multiple physical qubits and quantum error correction.QI NoteSimply having “created a logical qubit” does not necessarily mean fault-tolerant quantum computing (FTQC) has been achieved. One should verify logical error rates, operational/gate performance, and scalability., the company evaluated more than 31.5 million quantum operations and reports that, under standard operating noise assumptions, the increase in execution time due to decoding—called a “stretch”—was as small as 0.02%. ✍️ Quantum Index Analysis The technical and commercial significance behind the announcement and evaluation points that are not obvious from numbers or headlines alone. Read our independent analysis ↓ Announcement summary Quantum error correctionQuantum error correction量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. requires a classical computationclassical computationClassical Computing / Classical Computation / Classical Computing / Classical ComputationA computation method that uses bits of 0 and 1; the form of computation performed by the computers commonly used today.QI NoteUsed as a point of comparison with quantum computing, but it can encompass CPUs, GPUs, supercomputers, and specialized algorithms, so care should be taken about the conditions of comparison. step to analyze information from qubitsqubitsQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. and identify errors—this is the decoding process. If decoding cannot keep up with quantum computation, it can force the quantum system to wait. IonQ combined two types of decoders into a single configuration and ran them on a single standard CPU for the evaluation. The benchmark circuit simulated up to 408 logical qubits, representing 88 memory blocks and magic-state factories. The benchmark covered more than 31.5 million quantum operations. According to the company, under standard operating noise assumptions, the execution-time increase from decoding—referred to as a “stretch”—was as low as 0.02%. The research results are available on arXiv, and IonQ positions this work as a supporting element for its proprietary Walking Cat architectureWalking Cat architectureWalking Catアーキテクチャ / Walking Cat ArchitectureA fault-tolerant quantum computing architecture for trapped-ion quantum computers proposed by researchers including IonQ. It performs logical operations by leveraging quantum LDPC codes and cat states.QI NoteIt should be considered as a system-level design that includes not only the number of physical qubits but also the chosen error-correcting code, the number of logical qubits, logical gate speeds, and other aspects. At present it is an architecture based on proposals and simulations, and is not the name of a completed, operational device.. Note that the evaluation used simulated circuits; the announcement does not include results from running on quantum hardware of the same scale. Key points • Tested an end-to-end, real-time quantum error-correction decoder running on a single commercial CPU • Evaluated using circuits that simulated up to 408 logical qubits with 88 memory blocks and magic-state factories • The benchmark covered more than 31.5 million quantum operations • Under standard operating noise assumptions, decoding increased execution time by as little as 0.02% • IonQ frames this result as a validation of components for an industrial-scale system targeting thousands of qubits Technical and business implications From a technical perspective, the significance lies in performing the classical decoding step—a potential bottleneck for fault-tolerant quantum computingfault-tolerant quantum computingFTQC / Fault-Tolerant Quantum Computing / FTQCA method for future large-scale quantum computing that uses quantum error correction to allow correct computation to continue even when physical errors occur.QI NoteA demonstration of quantum error correction is not the same as realizing FTQC. Logical error rates, the number of physical qubits required, logical gate performance, and so on are important.—with low latency under simulated conditions that cover hundreds of logical qubits and tens of millions of operations. If decoding can be handled on a single CPU, it could reduce the classical hardware configuration and operational burden as quantum systems scale. From a business viewpoint, the result serves as a verification of components aimed at IonQ’s roadmap toward platforms with thousands of logical qubits. However, the company has not disclosed operation on real hardware at this scale, deployment costs, timelines for commercial system integration, or comparisons with other decoding approaches, so commercial viability cannot be assessed at this stage. What to watch next The next key question is whether the same-scale decoding can be sustained when connected to actual quantum hardware. Metrics to watch include latency and correction performance under different noise conditions, independent reproducibility, and comparisons with alternative approaches. It will also be important to monitor integration progress with the Walking Cat architecture and whether costs and delivery timelines for commercial deployment become concrete. ✍️ Quantum Index Analysis The notable outcome of this work is that IonQ, assuming its proposed fault-tolerant configuration called Walking Cat, was able to process in real time on a single commercial CPU the error-correction data required for quantum computations at the 408-logical-qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. scale. The paper reports evaluation on a 12-core Apple M4 Max, covering error estimation as well as updates to the error model and processing of logical measurement results as the computation progresses. The implication is that, when scaling quantum computers, it may not always be necessary to add large numbers of GPUs or dedicated decoders on the classical side—a point with both technical and cost significance. That said, the scale figures require clear caveats. Although IonQ’s press release does not state this, the paper assumes a device comprising 11,680 physical qubits (https://arxiv.org/html/2608.25027v2?utm_source=chatgpt.com). That configuration corresponds to 68 memory blocks holding 408 logical qubitslogical qubitsLogical Qubit / Logical QubitA unit of information treated as a single qubit protected from errors by using multiple physical qubits and quantum error correction.QI NoteSimply having “created a logical qubit” does not necessarily mean fault-tolerant quantum computing (FTQC) has been achieved. One should verify logical error rates, operational/gate performance, and scalability. and 20 magic-state factories. The company did not run 11,680 physical qubitsphysical qubitsPhysical Qubit / Physical QubitIndividual qubits that are physically created and manipulated on a quantum processor. They are also used to form logical qubits.QI NoteA large number of physical qubits does not by itself indicate practical computational capability. Error rates, connectivity, and the number of physical qubits required per logical qubit are also important. to create 408 logical qubits on hardware; rather, the study simulated the decoding workload that would arise for the assumed device and measured the decoding time on a CPU. Also, the statement that the “increase in execution time was as little as 0.02%” does not mean quantum computations reach that much higher fidelity after error correction. It refers to the percentage increase in runtime caused by holding the quantum computation while decoding catches up. In the 408-logical-qubit benchmark, changing the assumed two-qubit gate error rate from 10−410^{-4} to 5×10−45\times10^{-4} increases that figure from 0.02% to 0.72%. The low-latency result therefore needs to be interpreted alongside IonQ’s assumed hardware speeds and noise conditions. The result is also interesting relative to efforts to tightly couple quantum computers and GPUs. In a verification by Diraq and Iceberg Quantum of Pinnacle, NVIDIA’s CUDA-Q Logical was used to design how an error-correction scheme is laid out on spin qubits and to estimate the required number of physical qubits. However, that work did not demonstrate real-time decoding of error information streamed from an operating quantum computer to a GPU. The two efforts are not directly comparable: Diraq’s work addresses future device design, while IonQ’s work evaluates CPU decoding load when running an assumed device. If IonQ’s approach can perform decoding with CPUs alone, NVIDIA’s approach of using GPUs for error correction may not be necessary for every quantum computer. At the same time, CUDA-Q also serves roles in design, simulation, and bridging quantum and classical computationclassical computationClassical Computing / Classical Computation / Classical Computing / Classical ComputationA computation method that uses bits of 0 and 1; the form of computation performed by the computers commonly used today.QI NoteUsed as a point of comparison with quantum computing, but it can encompass CPUs, GPUs, supercomputers, and specialized algorithms, so care should be taken about the conditions of comparison., so this result does not eliminate the value of broader collaboration with NVIDIA. Additionally, the error-correction cycle assumed in IonQ’s paper is 1–5 milliseconds; the findings do not directly apply to schemes that demand shorter processing times. Reports said IonQ’s stock rose about 7% in after-hours trading following the announcement. However, the paper has been available since August, and this announcement does not mean large-scale quantum hardware or a commercial fault-tolerant quantum computerfault-tolerant quantum computerFTQC / Fault-Tolerant Quantum Computing / FTQCA method for future large-scale quantum computing that uses quantum error correction to allow correct computation to continue even when physical errors occur.QI NoteA demonstration of quantum error correction is not the same as realizing FTQC. Logical error rates, the number of physical qubits required, logical gate performance, and so on are important. is complete. Market reactions likely reflect expectations for the future. The next test will be whether the assumed physical qubit count, error rates, and operating speeds can be achieved on hardware and whether the same decoding performance and sufficiently low logical error rates can be maintained when the quantum hardware is connected to a CPU. NETWORKSee the industry network around IonQ → (/qi-network/) Related articles • Cleveland Clinic, RIKEN and IBM shortlisted for Gordon Bell Prize for quantum–HPC chemistry; processed a 12,635-atom system (https://en.quantumindex.jp/cleveland-clinic-riken-ibm-gordon-bell-finalists-2026/) • IonQ resource estimate for breaking secp256k1 with Shor’s algorithm: 19,397 physical qubits, 25.7 days (https://en.quantumindex.jp/ionq-secp256k1-fault-tolerant-resource-estimate/) • Photonic cuts logical-operation overhead with QLDPC “SHYPS,” compares to surface code in Nature Communications paper (https://en.quantumindex.jp/photonic-shyps-qldpc-nature-communications/) Sources Read the original announcement (https://www.ionq.com/news/ionq-demonstrates-industrys-first-end-to-end-real-time-quantum-error-decoder) If you found this article useful, please consider sharing it. ──────────────────── 【AI Evaluation Request】 Evaluate the following article critically, not based on the quality of its writing, but on its **original informational value as a specialist publication**. Do not give a high rating to summaries, paraphrases, explanations of technical terms, or generic observations such as "this will be worth watching" or "the timeline remains uncertain" if they could easily be produced by a general-purpose generative AI, even if they are well written. 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IonQ announced it has developed an end-to-end, real-time quantum error-correction decoder that runs on a single commercial CPU and says it successfully tested the system. Using benchmark circuits that simulated up to 408 logical qubitslogical qubitsLogical Qubit / Logical QubitA unit of information treated as a single qubit protected from errors by using multiple physical qubits and quantum error correction.QI NoteSimply having “created a logical qubit” does not necessarily mean fault-tolerant quantum computing (FTQC) has been achieved. One should verify logical error rates, operational/gate performance, and scalability., the company evaluated more than 31.5 million quantum operations and reports that, under standard operating noise assumptions, the increase in execution time due to decoding—called a “stretch”—was as small as 0.02%.

Announcement summary

Quantum error correctionQuantum error correction量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. requires a classical computationclassical computationClassical Computing / Classical Computation / Classical Computing / Classical ComputationA computation method that uses bits of 0 and 1; the form of computation performed by the computers commonly used today.QI NoteUsed as a point of comparison with quantum computing, but it can encompass CPUs, GPUs, supercomputers, and specialized algorithms, so care should be taken about the conditions of comparison. step to analyze information from qubitsqubitsQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. and identify errors—this is the decoding process. If decoding cannot keep up with quantum computation, it can force the quantum system to wait. IonQ combined two types of decoders into a single configuration and ran them on a single standard CPU for the evaluation. The benchmark circuit simulated up to 408 logical qubits, representing 88 memory blocks and magic-state factories. The benchmark covered more than 31.5 million quantum operations. According to the company, under standard operating noise assumptions, the execution-time increase from decoding—referred to as a “stretch”—was as low as 0.02%. The research results are available on arXiv, and IonQ positions this work as a supporting element for its proprietary Walking Cat architectureWalking Cat architectureWalking Catアーキテクチャ / Walking Cat ArchitectureA fault-tolerant quantum computing architecture for trapped-ion quantum computers proposed by researchers including IonQ. It performs logical operations by leveraging quantum LDPC codes and cat states.QI NoteIt should be considered as a system-level design that includes not only the number of physical qubits but also the chosen error-correcting code, the number of logical qubits, logical gate speeds, and other aspects. At present it is an architecture based on proposals and simulations, and is not the name of a completed, operational device.. Note that the evaluation used simulated circuits; the announcement does not include results from running on quantum hardware of the same scale.

Key points

• Tested an end-to-end, real-time quantum error-correction decoder running on a single commercial CPU
• Evaluated using circuits that simulated up to 408 logical qubits with 88 memory blocks and magic-state factories
• The benchmark covered more than 31.5 million quantum operations
• Under standard operating noise assumptions, decoding increased execution time by as little as 0.02%
• IonQ frames this result as a validation of components for an industrial-scale system targeting thousands of qubits

Technical and business implications

From a technical perspective, the significance lies in performing the classical decoding step—a potential bottleneck for fault-tolerant quantum computingfault-tolerant quantum computingFTQC / Fault-Tolerant Quantum Computing / FTQCA method for future large-scale quantum computing that uses quantum error correction to allow correct computation to continue even when physical errors occur.QI NoteA demonstration of quantum error correction is not the same as realizing FTQC. Logical error rates, the number of physical qubits required, logical gate performance, and so on are important.—with low latency under simulated conditions that cover hundreds of logical qubits and tens of millions of operations. If decoding can be handled on a single CPU, it could reduce the classical hardware configuration and operational burden as quantum systems scale.

From a business viewpoint, the result serves as a verification of components aimed at IonQ’s roadmap toward platforms with thousands of logical qubits. However, the company has not disclosed operation on real hardware at this scale, deployment costs, timelines for commercial system integration, or comparisons with other decoding approaches, so commercial viability cannot be assessed at this stage.

What to watch next

The next key question is whether the same-scale decoding can be sustained when connected to actual quantum hardware. Metrics to watch include latency and correction performance under different noise conditions, independent reproducibility, and comparisons with alternative approaches. It will also be important to monitor integration progress with the Walking Cat architecture and whether costs and delivery timelines for commercial deployment become concrete.

✍️ Quantum Index Analysis

The notable outcome of this work is that IonQ, assuming its proposed fault-tolerant configuration called Walking Cat, was able to process in real time on a single commercial CPU the error-correction data required for quantum computations at the 408-logical-qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. scale. The paper reports evaluation on a 12-core Apple M4 Max, covering error estimation as well as updates to the error model and processing of logical measurement results as the computation progresses. The implication is that, when scaling quantum computers, it may not always be necessary to add large numbers of GPUs or dedicated decoders on the classical side—a point with both technical and cost significance.

That said, the scale figures require clear caveats. Although IonQ’s press release does not state this, the paper assumes a device comprising 11,680 physical qubits. That configuration corresponds to 68 memory blocks holding 408 logical qubitslogical qubitsLogical Qubit / Logical QubitA unit of information treated as a single qubit protected from errors by using multiple physical qubits and quantum error correction.QI NoteSimply having “created a logical qubit” does not necessarily mean fault-tolerant quantum computing (FTQC) has been achieved. One should verify logical error rates, operational/gate performance, and scalability. and 20 magic-state factories. The company did not run 11,680 physical qubitsphysical qubitsPhysical Qubit / Physical QubitIndividual qubits that are physically created and manipulated on a quantum processor. They are also used to form logical qubits.QI NoteA large number of physical qubits does not by itself indicate practical computational capability. Error rates, connectivity, and the number of physical qubits required per logical qubit are also important. to create 408 logical qubits on hardware; rather, the study simulated the decoding workload that would arise for the assumed device and measured the decoding time on a CPU.

Also, the statement that the “increase in execution time was as little as 0.02%” does not mean quantum computations reach that much higher fidelity after error correction. It refers to the percentage increase in runtime caused by holding the quantum computation while decoding catches up. In the 408-logical-qubit benchmark, changing the assumed two-qubit gate error rate from $10^{-4}$ to $5\times10^{-4}$ increases that figure from 0.02% to 0.72%. The low-latency result therefore needs to be interpreted alongside IonQ’s assumed hardware speeds and noise conditions.

The result is also interesting relative to efforts to tightly couple quantum computers and GPUs. In a verification by Diraq and Iceberg Quantum of Pinnacle, NVIDIA’s CUDA-Q Logical was used to design how an error-correction scheme is laid out on spin qubits and to estimate the required number of physical qubits. However, that work did not demonstrate real-time decoding of error information streamed from an operating quantum computer to a GPU. The two efforts are not directly comparable: Diraq’s work addresses future device design, while IonQ’s work evaluates CPU decoding load when running an assumed device.

If IonQ’s approach can perform decoding with CPUs alone, NVIDIA’s approach of using GPUs for error correction may not be necessary for every quantum computer. At the same time, CUDA-Q also serves roles in design, simulation, and bridging quantum and classical computationclassical computationClassical Computing / Classical Computation / Classical Computing / Classical ComputationA computation method that uses bits of 0 and 1; the form of computation performed by the computers commonly used today.QI NoteUsed as a point of comparison with quantum computing, but it can encompass CPUs, GPUs, supercomputers, and specialized algorithms, so care should be taken about the conditions of comparison., so this result does not eliminate the value of broader collaboration with NVIDIA. Additionally, the error-correction cycle assumed in IonQ’s paper is 1–5 milliseconds; the findings do not directly apply to schemes that demand shorter processing times.

Reports said IonQ’s stock rose about 7% in after-hours trading following the announcement. However, the paper has been available since August, and this announcement does not mean large-scale quantum hardware or a commercial fault-tolerant quantum computerfault-tolerant quantum computerFTQC / Fault-Tolerant Quantum Computing / FTQCA method for future large-scale quantum computing that uses quantum error correction to allow correct computation to continue even when physical errors occur.QI NoteA demonstration of quantum error correction is not the same as realizing FTQC. Logical error rates, the number of physical qubits required, logical gate performance, and so on are important. is complete. Market reactions likely reflect expectations for the future. The next test will be whether the assumed physical qubit count, error rates, and operating speeds can be achieved on hardware and whether the same decoding performance and sufficiently low logical error rates can be maintained when the quantum hardware is connected to a CPU.

NETWORKSee the industry network around IonQ →

Related articles

• Cleveland Clinic, RIKEN and IBM shortlisted for Gordon Bell Prize for quantum–HPC chemistry; processed a 12,635-atom system
• IonQ resource estimate for breaking secp256k1 with Shor’s algorithm: 19,397 physical qubits, 25.7 days
• Photonic cuts logical-operation overhead with QLDPC “SHYPS,” compares to surface code in Nature Communications paper

Sources

Read the original announcement