SEEQC and NVIDIA simulation shows ~50% cut in QEC latency and logical error rate

【Article Title】 SEEQC and NVIDIA simulation shows ~50% cut in QEC latency and logical error rate 【Article Body】 AI TRANSLATION This article is an AI-generated translation of the original Japanese article. For the authoritative version, please refer to the original. Read the original Japanese article → (https://quantumindex.jp/seeqc-qec-decoder-nvidia-ising-nvqlink/) SEEQC has released verification results for a multi-stage quantum error correctionquantum error correction量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. (QEC) decoding architecture that combines a chip-based pre-decoder with NVIDIA Ising. In simulation, the configuration reduced decode latency and logical error rate by roughly 50% compared with a setup using NVIDIA Ising alone as the pre-decoder. ✍️ Quantum Index Analysis The analysis explains the technical and commercial implications behind the announcement and highlights evaluation points that are not obvious from the numbers and headlines alone. Read our independent analysis ↓ Summary of the announcement In the tested architecture, SEEQC’s dedicated pre-decoder placed near the QPUQPUQuantum Processor / Quantum Processor / Quantum Processing Unit / QPUThe central part of the hardware that houses qubits and performs quantum computational operations such as quantum gates and measurements.QI NoteThe performance of a QPU cannot be judged by the number of qubits alone. Gate fidelity, connectivity, speed, error rates, and other factors must be considered together. is combined with decoding performed by NVIDIA Ising in a GPU-accelerated environment. SEEQC Digital Link and NVIDIA NVQLink were used as the low-latency communication backbone connecting the quantum environment and the GPU compute environment. The evaluation was conducted on simulations of quantum processors and architectures that include realistic decoder delays at scale. By performing part of the processing near the QPU, the design reduces the amount of information sent to higher-level classical compute resources and accelerates critical decoding tasks. SEEQC said its next step is to integrate the demonstrated components and realize chip-to-chip connections between quantum processors and advanced HPC infrastructure. Key points • Verified a multi-stage architecture combining SEEQC’s chip-based pre-decoder and NVIDIA Ising. • Compared with a configuration using NVIDIA Ising alone as the pre-decoder, the simulated setup reduced decode latency and logical error rate by about 50%. • Evaluation used a simulation environment accounting for decoder delays when scaling up. • SEEQC Digital Link and NVIDIA NVQLink provided the low-latency communication fabric between the quantum environment and GPU compute environment. • The next phase aims for chip-to-chip integration between quantum processors and HPC infrastructure. Technical and commercial significance In quantum error correction, decode latency and logical error rate are critical, and data movement between the QPU and classical compute resources becomes a scaling challenge. The results suggest that partitioning QEC processing between a dedicated digital processor near the QPU and GPU-based processing can help mitigate these burdens. From a business perspective, this approach could enable concrete designs for low-latency integration of quantum processors with GPU-accelerated HPC. However, the results are simulation-based; the company has not disclosed performance on real hardware, deployment costs, or a commercialization timeline. What to watch next The next critical question is whether chip-to-chip integration between quantum processors and HPC platforms can be realized in hardware and reproduce the latency and logical error rate improvements. Important evaluation criteria will include the effect when scaling qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. counts and processing size, and the actual reduction in data sent to higher-level compute resources. Additional points of interest are performance in quantum-AI workloads and whether the company publishes implementation conditions including deployment cost. ✍️ Quantum Index Analysis What stands out in this announcement is not only the headline figure of roughly 50% improvement in decode latency and logical error rate, but the architectural concept of distributing QECQEC量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. processing between a dedicated chip near the QPUQPUQuantum Processor / Quantum Processor / Quantum Processing Unit / QPUThe central part of the hardware that houses qubits and performs quantum computational operations such as quantum gates and measurements.QI NoteThe performance of a QPU cannot be judged by the number of qubits alone. Gate fidelity, connectivity, speed, error rates, and other factors must be considered together. and GPUs. As quantum computers scale, not only the classical compute required for error correction but also the volume of syndrome data and communication latency become severe challenges. Doing all processing on GPUs may be suboptimal; front-loading some preprocessing close to the QPU is a reasonable approach. SEEQC has been developing superconducting digital chip technology that moves functions traditionally handled by room-temperature control equipment into the ultra-low-temperature environment. In the development roadmap the company published in 2024 (development roadmap (https://www.quantumcomputinglab.cineca.it/wp-content/uploads/2024/03/Arzeo.pdf)), SEEQC classifies quantum computer systems into four generations. GenerationSystem namePhysical qubitPhysical qubitPhysical Qubit / Physical QubitIndividual qubits that are physically created and manipulated on a quantum processor. They are also used to form logical qubits.QI NoteA large number of physical qubits does not by itself indicate practical computational capability. Error rates, connectivity, and the number of physical qubits required per logical qubit are also important. countKey technologies / featuresDevelopment statusGeneration 1RedExternal reports of a 5-qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. systemReference system using conventional analog controlAnnounced as hardwareGeneration 2OrangeUnconfirmedSFQ digital control, signal multiplexingAnnounced as hardwareGeneration 3YellowNot disclosedZ control with SFQ, digital readout, QEC-capableUnder development; integrated system completion not confirmedGeneration 4GreenNot disclosedLogical quantum computer integrating an SFQ decoderConceptual / development planning stage * Development status is based on publicly available information as of October 2026. The Red qubit count comes from external materials and is not confirmed in the official roadmap. For Yellow and later generations, it is important to distinguish between demonstrations of individual technologies and the completion of an integrated system. This result can be seen as contributing to the technologies needed for the Green generation’s goal of integrating QEC processing on-chip. However, Green itself is not complete; the current validation remains simulation-based. The comparison was limited to a configuration using NVIDIA Ising alone as the pre-decoder; absolute latency values, logical error rates, and code sizes were not disclosed. GPU use in quantum error correction already extends across several stages. Riverlane used NVIDIA H100 to speed up decoder recalibration by up to 65× (https://en.quantumindex.jp/riverlane-gpu-qec-decoder-recalibration/) and reported up to a halving of logical error rates. However, Riverlane’s results focused mainly on decoder training and calibration, which differs from SEEQC’s approach of delegating real-time preprocessing near the QPU. The improvement figures from each company are not directly comparable. Separately, Qblox demonstrated low-latency connections between GPUs and quantum control hardware using NVIDIA NVQLink (https://en.quantumindex.jp/qblox-dgx-spark-nvqlink-integration/). Summarizing these efforts: Riverlane emphasizes decoder training and calibration; Qblox focuses on low-latency GPU–control hardware links; SEEQC emphasizes preprocessing on a dedicated chip near the QPU. These approaches are not mutually exclusive—future QEC systems may combine such technologies. This trend also relates to the infrastructure competition around the classical side of quantum computers involving NVIDIA and AMD. Classical processing needs for QEC are heterogeneous: large-scale parallel computing for decoder training and optimization differs from real-time processing under tight latency constraints. Even if NVIDIA GPUs form a core part of quantum compute infrastructure, not all workloads will consolidate on GPUs; role distribution among ASICs, FPGAs, and ultra-low-temperature digital circuits will matter. For SEEQC, the business opportunity may lie less in increasing qubit counts for its own QPUs than in establishing control and QEC infrastructure that can be integrated into other vendors’ quantum computers. Introducing a dedicated chip carries manufacturing and implementation costs as well as constraints such as power consumption and cooling load in ultra-low-temperature environments. Reproducing the simulation results on hardware and demonstrating advantages in system-level performance, power consumption, and cost compared with GPU-only or other dedicated decoder configurations will determine SEEQC’s technical and commercial assessment. NETWORKSee the quantum industry network → (/qi-network/) Related articles • Who will control the classical side of quantum computers? NVIDIA and AMD in the quantum compute infrastructure race (https://en.quantumindex.jp/quantum-classical-infrastructure-nvidia-amd/) • Qblox demonstrates low-latency connection to NVIDIA GPUs, expanding control infrastructure after Riverlane QEC demonstrations (https://en.quantumindex.jp/qblox-dgx-spark-nvqlink-integration/) • JIJ and Mitsubishi Electric to evaluate quantum linear solvers for thermal-fluid analysis—differentiation and practicality are key (https://en.quantumindex.jp/jij-mitsubishi-electric-hybrid-linear-solver-jhpc-quantum/) Source Read the original announcement (https://seeqc.com/resources/seeqc-demonstrates-quantum-error-correction-performance-gains-with-industry-first-digital-interface-optimized-decoder-architecture-using-nvidia-ising-and-nvqlink) If you found this article useful, please consider sharing it. ──────────────────── 【AI Evaluation Request】 Evaluate the following article critically, not based on the quality of its writing, but on its **original informational value as a specialist publication**. Do not give a high rating to summaries, paraphrases, explanations of technical terms, or generic observations such as "this will be worth watching" or "the timeline remains uncertain" if they could easily be produced by a general-purpose generative AI, even if they are well written. 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SEEQC has released verification results for a multi-stage quantum error correctionquantum error correction量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. (QEC) decoding architecture that combines a chip-based pre-decoder with NVIDIA Ising. In simulation, the configuration reduced decode latency and logical error rate by roughly 50% compared with a setup using NVIDIA Ising alone as the pre-decoder.

Summary of the announcement

In the tested architecture, SEEQC’s dedicated pre-decoder placed near the QPUQPUQuantum Processor / Quantum Processor / Quantum Processing Unit / QPUThe central part of the hardware that houses qubits and performs quantum computational operations such as quantum gates and measurements.QI NoteThe performance of a QPU cannot be judged by the number of qubits alone. Gate fidelity, connectivity, speed, error rates, and other factors must be considered together. is combined with decoding performed by NVIDIA Ising in a GPU-accelerated environment. SEEQC Digital Link and NVIDIA NVQLink were used as the low-latency communication backbone connecting the quantum environment and the GPU compute environment. The evaluation was conducted on simulations of quantum processors and architectures that include realistic decoder delays at scale. By performing part of the processing near the QPU, the design reduces the amount of information sent to higher-level classical compute resources and accelerates critical decoding tasks. SEEQC said its next step is to integrate the demonstrated components and realize chip-to-chip connections between quantum processors and advanced HPC infrastructure.

Key points

• Verified a multi-stage architecture combining SEEQC’s chip-based pre-decoder and NVIDIA Ising.
• Compared with a configuration using NVIDIA Ising alone as the pre-decoder, the simulated setup reduced decode latency and logical error rate by about 50%.
• Evaluation used a simulation environment accounting for decoder delays when scaling up.
• SEEQC Digital Link and NVIDIA NVQLink provided the low-latency communication fabric between the quantum environment and GPU compute environment.
• The next phase aims for chip-to-chip integration between quantum processors and HPC infrastructure.

Technical and commercial significance

In quantum error correction, decode latency and logical error rate are critical, and data movement between the QPU and classical compute resources becomes a scaling challenge. The results suggest that partitioning QEC processing between a dedicated digital processor near the QPU and GPU-based processing can help mitigate these burdens. From a business perspective, this approach could enable concrete designs for low-latency integration of quantum processors with GPU-accelerated HPC. However, the results are simulation-based; the company has not disclosed performance on real hardware, deployment costs, or a commercialization timeline.

What to watch next

The next critical question is whether chip-to-chip integration between quantum processors and HPC platforms can be realized in hardware and reproduce the latency and logical error rate improvements. Important evaluation criteria will include the effect when scaling qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. counts and processing size, and the actual reduction in data sent to higher-level compute resources. Additional points of interest are performance in quantum-AI workloads and whether the company publishes implementation conditions including deployment cost.

✍️ Quantum Index Analysis

What stands out in this announcement is not only the headline figure of roughly 50% improvement in decode latency and logical error rate, but the architectural concept of distributing QECQEC量子誤り訂正 / Quantum Error Correction / QECA technique that distributes information across multiple physical qubits and detects and corrects errors without directly disturbing the quantum state.QI NoteSimply implementing it does not automatically provide practical fault tolerance. What matters is whether the logical error rate is improved relative to the physical error rate. processing between a dedicated chip near the QPUQPUQuantum Processor / Quantum Processor / Quantum Processing Unit / QPUThe central part of the hardware that houses qubits and performs quantum computational operations such as quantum gates and measurements.QI NoteThe performance of a QPU cannot be judged by the number of qubits alone. Gate fidelity, connectivity, speed, error rates, and other factors must be considered together. and GPUs. As quantum computers scale, not only the classical compute required for error correction but also the volume of syndrome data and communication latency become severe challenges. Doing all processing on GPUs may be suboptimal; front-loading some preprocessing close to the QPU is a reasonable approach.

SEEQC has been developing superconducting digital chip technology that moves functions traditionally handled by room-temperature control equipment into the ultra-low-temperature environment. In the development roadmap the company published in 2024 (development roadmap), SEEQC classifies quantum computer systems into four generations.

Generation	System name	Physical qubitPhysical qubitPhysical Qubit / Physical QubitIndividual qubits that are physically created and manipulated on a quantum processor. They are also used to form logical qubits.QI NoteA large number of physical qubits does not by itself indicate practical computational capability. Error rates, connectivity, and the number of physical qubits required per logical qubit are also important. count	Key technologies / features	Development status
Generation 1	Red	External reports of a 5-qubitqubitQubit / Quantum Bit / QubitThe basic unit of information in a quantum computer. It can represent not only 0 or 1 but also a quantum state that is a superposition of them.QI NoteHaving more qubits does not necessarily mean higher performance. Error rates, connectivity, coherence time, and the number of logical qubits are also important. system	Reference system using conventional analog control	Announced as hardware
Generation 2	Orange	Unconfirmed	SFQ digital control, signal multiplexing	Announced as hardware
Generation 3	Yellow	Not disclosed	Z control with SFQ, digital readout, QEC-capable	Under development; integrated system completion not confirmed
Generation 4	Green	Not disclosed	Logical quantum computer integrating an SFQ decoder	Conceptual / development planning stage

* Development status is based on publicly available information as of October 2026. The Red qubit count comes from external materials and is not confirmed in the official roadmap. For Yellow and later generations, it is important to distinguish between demonstrations of individual technologies and the completion of an integrated system.

This result can be seen as contributing to the technologies needed for the Green generation’s goal of integrating QEC processing on-chip. However, Green itself is not complete; the current validation remains simulation-based. The comparison was limited to a configuration using NVIDIA Ising alone as the pre-decoder; absolute latency values, logical error rates, and code sizes were not disclosed.

GPU use in quantum error correction already extends across several stages. Riverlane used NVIDIA H100 to speed up decoder recalibration by up to 65× and reported up to a halving of logical error rates. However, Riverlane’s results focused mainly on decoder training and calibration, which differs from SEEQC’s approach of delegating real-time preprocessing near the QPU. The improvement figures from each company are not directly comparable.

Separately, Qblox demonstrated low-latency connections between GPUs and quantum control hardware using NVIDIA NVQLink. Summarizing these efforts: Riverlane emphasizes decoder training and calibration; Qblox focuses on low-latency GPU–control hardware links; SEEQC emphasizes preprocessing on a dedicated chip near the QPU. These approaches are not mutually exclusive—future QEC systems may combine such technologies.

This trend also relates to the infrastructure competition around the classical side of quantum computers involving NVIDIA and AMD. Classical processing needs for QEC are heterogeneous: large-scale parallel computing for decoder training and optimization differs from real-time processing under tight latency constraints. Even if NVIDIA GPUs form a core part of quantum compute infrastructure, not all workloads will consolidate on GPUs; role distribution among ASICs, FPGAs, and ultra-low-temperature digital circuits will matter.

For SEEQC, the business opportunity may lie less in increasing qubit counts for its own QPUs than in establishing control and QEC infrastructure that can be integrated into other vendors’ quantum computers. Introducing a dedicated chip carries manufacturing and implementation costs as well as constraints such as power consumption and cooling load in ultra-low-temperature environments. Reproducing the simulation results on hardware and demonstrating advantages in system-level performance, power consumption, and cost compared with GPU-only or other dedicated decoder configurations will determine SEEQC’s technical and commercial assessment.

NETWORKSee the quantum industry network →

Related articles

• Who will control the classical side of quantum computers? NVIDIA and AMD in the quantum compute infrastructure race
• Qblox demonstrates low-latency connection to NVIDIA GPUs, expanding control infrastructure after Riverlane QEC demonstrations
• JIJ and Mitsubishi Electric to evaluate quantum linear solvers for thermal-fluid analysis—differentiation and practicality are key

Source

Read the original announcement