QUDORA adopts QC Design’s Plaquette to evaluate fault-tolerant designs for NFQC ion-trap processors
On December 3, 2025, QUDORA announced it has introduced QC Design’s quantum design automation platform Plaquette into its research and development process. For its ion-trap quantum processors that use the proprietary Near Field Quantum Control (NFQC) technique, the company will evaluate the full fault-tolerant architecture—including quantum error-correcting codes and control sequences—during the design phase.
Announcement overview
Plaquette is a design automation platform for simulating, analyzing, and optimizing fault-tolerant quantum-computing architectures. According to QC Design, it can model more than 20 types of hardware imperfections and includes a library of quantum error-correcting codes and decoders.
QUDORA’s NFQC controls ion qubits using on‑chip near-field microwaves instead of conventional laser control. The approach is intended for integration into complex two-dimensional arrays using semiconductor manufacturing techniques. With this deployment, QUDORA will explore error-correcting codes and control procedures suited to this hardware configuration and advance evaluation and optimization prior to moving from design to fabrication.
Key points
- QC Design’s Plaquette has been integrated into QUDORA’s R&D process
- It will be used to evaluate the full fault-tolerant design, including error-correcting codes and control sequences
- QUDORA’s NFQC controls ion qubits via on‑chip near-field microwaves
- Specific error rates, logical qubit counts, implementation costs, and timelines for commercialization have not been disclosed
Technical and business implications
Technically, this effort represents not only hardware scalability via semiconductor processes but also an attempt to assess the entire system—including quantum error correction—before manufacturing. If NFQC‑specific constraints and imperfections can be reflected in the design, Plaquette can provide a way to explore logical qubit layouts that account for hardware efficiency. From a business perspective, using a dedicated software platform reduces the burden of building an equivalent in‑house evaluation environment and aims to lower design risk and development time for a fault‑tolerant architecture. However, the announcement did not include quantitative results demonstrating the impact.
What to watch next
Going forward, the focus will be on whether Plaquette’s evaluation results are presented quantitatively—e.g., physical error rates, logical error rates, and the number of qubits required for error correction. It will also be important to see whether design optimizations are validated on NFQC hardware or in two‑dimensional arrays, and whether concrete steps from design to fabrication are outlined. In addition, clarification of development timelines for fault‑tolerant operation and the scope of collaboration between the two companies will be key indicators of business progress.
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